Digital images sensors include an array of differentiated photosensitive elements. Depending upon the application, the sensor may have a one-dimensional array or a two-dimensional array of the photosensitive elements. For each element, an electrical charge is generated during each sampling time period, with the electrical charge being proportional to the intensity of light received at the element during the sampling time period.
One type of sensor array utilizes photo diodes to generate the signals that are responsive to received light. FIG. 1 illustrates a single photo diode 10 formed on a pixel interconnection structure 12. The interconnection structure is typically formed on a substrate, such as a semiconductor substrate, using conventional CMOS (Complementary Metal Oxide Silicon) fabrication techniques. A conductive via 14 extends through the interconnection structure to conduct signals from the photo diode. The interconnection structure may be silicon oxide or silicon nitride having tungsten vias 14.
Atop the interconnection structure 12 are three amorphous silicon layers 16, 18 and 20 which form a PIN diode structure. The PIN diode structure is referred to as an “elevated” sensor element, since it is positioned above the surface of the supporting substrate. A lowermost amorphous silicon layer 16 contains an N-type dopant to form one electrode. Atop this bottom electrode is an intrinsic layer 18. The third layer 20 is a P-doped amorphous silicon layer. While only one photo diode is shown in FIG. 1, an array of closely spaced photo diodes is simultaneously fabricated. A substantially transparent top conductive layer 22 provides a common connection to all of the photo diodes. One available material for forming the top conductive layer is ITO (Indium Tin Oxide).
There are a number of issues which must be considered in the design and fabrication of sensor arrays. Defects or impurities along the interfaces of two of the amorphous silicon layers 16, 18 and 20 will degrade performance. If an interface is damaged or is laced with impurities, intended blocking and contact properties will be adversely affected. Ideally, pristine interfaces between the imaging layers are preserved. However, the traditional fabrication techniques for differentiating the pixels within the image array require at least one of the amorphous silicon layers to be patterned in a manner which requires exposure of a layer surface to the ambience and to contamination processing.
Another concern is that defects in the amorphous silicon layers 16, 18 and 20 may be formed by exposure to intense radiation during and after fabrication, such as by the SWE (Staebter-Wronski Effect). Defects and/or impurities lead to inter-pixel leakage during the operation of the image sensor array.
Yet another concern is that the layer patterning which typically occurs prior to deposition of the top conductive layer 22 must consider the step coverage of the material used to form the top conductive layer. Thus, if the upper amorphous silicon layer 20 is patterned in order to differentiate the adjacent pixels, the step coverage of the top conductive layer 22 must be sufficient to conformally cover the resulting topology, or there will be electrical discontinuity within the array. It is difficult to reliably and controllably pattern the upper amorphous layer without encroaching upon or damaging the intrinsic imaging layer 18. Moreover, if only the upper amorphous silicon layer 20 is patterned, the lowermost amorphous silicon layer 16 will be common to all of the pixels, causing some pixel-to-pixel shorting.
FIGS. 2-5 illustrate process steps described in U.S. Pat. No. 5,936,261 to Ma et al., which is assigned to the assignee of the present invention. As shown in FIG. 2, in addition to the three amorphous silicon layers 16, 18 and 20, there is an inner metal layer 24. The inner metal layer is an optional layer that has a low resistivity, enhancing the connection between the conductive vias 14 and the photo diode structure defined by the three amorphous silicon layers. Below the interconnection structure 12 is a substrate 26 and an intermediate interconnection structure 28. Often, the substrate includes CMOS sense circuitry and signal processing circuitry. The intermediate interconnection structure 28 includes pixel-specific conductive paths 30 aligned with the vias 14 and includes an additional conductive path 32 that is subsequently connected to the transparent top conductive layer, not shown. The intermediate interconnection structure 28 may be formed of a subtractive metal or may be formed of a single or dual damascene material.
In FIG. 3, the inner metal layer 24 and the three amorphous silicon layers 16, 18 and 20 have been wet or dry etched in order to form the desired pattern of photo diodes 34 and 36. Then, in FIG. 4, an insulating layer 38 is deposited. As one possibility, silicon dioxide or silicon nitride may be deposited using CVD (Chemical Vapor Deposition) processing. The insulating layer fills the gaps between the photo diodes.
In FIG. 5, the upper surface is planarized by polishing or etching the insulating layer 38. While not shown, the insulating layer may be patterned to expose the conductive via 40 aligned with the path 32 and the transparent top conductive layer may be formed to interconnect all of the photo diodes 34 and 36 to the via 40. The resulting structure is shown in FIG. 6.
A concern with the processing of FIGS. 2-5 is that it requires exacting tolerances with regard to the planarization from FIG. 4 to FIG. 5, such that the upper amorphous silicon layer 20 is not thinned abnormally across the pixel array. Different post-polish or post-etch thicknesses of layer 20 will affect the spectral response across the pixel array. A relaxation of the required tolerances would increase the fabrication yields in forming image sensor arrays.
Another approach to defining the array of photo diodes is to merely pattern the lower electrode or the lower amorphous silicon layer of the different pixels. For example, in FIG. 2, this would result in only the N-type layer 16 or the inner metal layer 24 being patterned, while the upper amorphous silicon layers 18 and 20 are blanket deposited. However, as previously noted, there is a susceptibility to introducing physical defects and/or impurities when the patterning techniques are applied while one of the interface surfaces of the amorphous silicon layers is exposed.
Another approach is to form trenches between adjacent photo diodes before the amorphous silicon layers are formed. Then, when the lower electrode layer is deposited, the layer will “pinch off”, at the inter-pixel trenches, thereby isolating the photo diodes. However, this pinch off approach does not isolate the intrinsic amorphous silicon layer, which is the imaging layer, so that extremely pure and stable intrinsic film is required. At different light-induced voltages, parasitic transistor devices can be undesirably formed between the photo diodes. These parasitic transistor devices promote inter-pixel leakage. An extension of the this approach is to pattern both the upper and lower electrodes (layers 16 and 20 in FIG. 1) to provide greater isolation. Again, inter-pixel leakage will occur within the unpatterned intrinsic semiconductor layer 18, which is the imaging layer. Moreover, as previously noted, it is difficult to reliably and controllably pattern the upper electrode layer without encroaching upon or damaging the intrinsic imaging layer. The patterned upper electrode may also introduce successive topology that results in poor conformality of the transparent top conductive layer. Thus, while known approaches provide desired results when sufficient care is taken, each known approach carries risks.